Microchip Technology ATSAM4C32 32-Bit Microcontroller

Microchip Technology ATSAM4C32 32-Bit Microcontroller (MCU) is a System-on-Chip (SoC) solution for smart energy applications built around two high-performance Arm® Cortex®-M4 RISC processors. The ATSAM4C32 operates at a maximum speed of 120MHz and features 2Mbytes of embedded Flash, 304Kbytes of SRAM, and an on-chip cache for each core. The dual Arm Cortex-M4 architecture allows for integrating an application layer, communications layers, and security functions in a single device, with the ability to extend program and data memory via a 16-bit external bus interface.

The peripheral set of the ATSAM4C32 MCU includes an advanced cryptographic engine, anti-tamper, Floating Point Unit (FPU), a USB Full-speed Host/Device port, five USARTs, two UARTs, two TWIs, and up to seven SPIs. The device also incorporates a PWM timer, two 3-channel general-purpose 16-bit timers, calibrated low-power RTC running on the backup domain down to 0.5µA, and a 50 x 6 segmented LCD controller.
The SAM4C series is a scalable platform providing, alongside Microchip’s industry-leading SAM4 standard microcontrollers, unprecedented cost structure, performance, and flexibility to smart meter designers worldwide.

Features

Application/master core
- Arm Cortex-M4 running at up to 120MHz
- Memory Protection Unit (MPU)
- DSP instruction
- Thumb®-2 instruction set
- Instruction and data cache controller with 2Kbytes cache memory
- Memories
  - Up to 2Mbytes of embedded Flash for program code (I-Code bus) and program data (D-Code bus) with built-in ECC (2-bit error detection and 1-bit correction per 128 bits)
  - Up to 256Kbytes of embedded SRAM (SRAM0) for program data (System bus)
  - 8Kbytes of ROM with embedded bootloader routines (UART) and In-Application Programming (IAP) routines
Coprocessor (provides the ability to separate application, communication, or metrology functions)
- Arm Cortex-M4F running at up to 120MHz
- IEEE® 754 compliant, single-precision Floating-Point Unit (FPU)
- DSP instruction
- Thumb-2 instruction set
- Instruction and data cache controller with 2Kbytes of cache memory
- Memories
  - Up to 32Kbytes of embedded SRAM (SRAM1) for program code (I-Code bus) and program data (D-Code bus and system bus)
  - Up to 16Kbytes of embedded SRAM (SRAM2) for program data (system bus)
Symmetrical/asynchronous dual-core architecture
- Interrupt-based interprocessor communication
- Asynchronous clocking
- One interrupt controller (NVIC) for each core
- Each peripheral IRQ routed to each NVIC input
Shared system controller
- Power supply
  - Embedded core and LCD voltage regulator for single-supply operation
  - Power-on-Reset (POR), Brownout Detector (BOD), and Dual Watchdog for safe operation
  - Ultra-low-power Backup mode (<5µA Typical @ 25°C)
- Clock
  - 3MHz to 20MHz oscillator supporting crystal, ceramic resonator, or external clock; Clock failure detection also supported
  - Ultra-low-power 768kHz oscillator supporting crystal or external clock signal and frequency monitoring
  - High-precision 4/8/12MHz factory-trimmed internal RC oscillator with on-the-fly trimming capability
  - One high-frequency PLL up to 240MHz, one 8MHz PLL with internal 32kHz input, as a source for high-frequency PLL
  - Low-power slow clock internal RC oscillator as a permanent clock
- Ultra-low-power RTC with Gregorian and Persian _Calendar, Waveform Generation in Backup mode and Clock Calibration Circuitry for 768kHz Crystal Frequency Compensation Circuitry
- Up to 23 peripheral DMA (PDC) channels

Cryptography
- High-performance AES 128 to 256 with various modes (GCM, CBC, ECB, CFB, CBC-MAC, CTR)
- TRNG (up to 38Mbit/s stream, with tested Diehard and FIPS)
- Public Key Crypto accelerator and associated ROM library for RSA, ECC, DSA, ECDSA
- Integrity Check Module (ICM) based on Secure Hash Algorithm (SHA1, SHA224, SHA256), DMA-assisted
Safety
- Up to four physical anti-tamper detection I/Os with time stamping and immediate clear of general backup registers
- Security bit for device protection from JTAG accesses
Shared Peripherals
- One low-power segmented LCD controller
  - Display capacity of 50 segments and 6 common terminals
  - Software-selectable LCD output voltage (Contrast)
  - Low current consumption in Low-power mode
  - It can be used in Backup mode
- Up to five USARTs with ISO7816, IrDA®, RS-485, SPI, and Manchester Mode
- Two 2-wire UARTs with one UART (UART1) supporting optical transceiver providing an electrically isolated serial communication with hand-held equipment, such as calibrators, compliant with ANSI-C12.18 or IEC62056-21 norms
- Full-speed USB Host and Device Port (available only for SAM4C32E in a 144-pin package)
- Up to two 400kHz Master/Slave and Multi-Master Two-wire Interfaces (I²C compatible)
- Up to seven Serial Peripheral Interfaces (SPI)
- Two 3-channel 16-bit Timer/Counters with Capture, Waveform, Compare, and PWM modes
- Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor
- 4-channel 16-bit Pulse Width Modulator
- 32-bit Real-time Timer
Analog Conversion Block
- 8-channel, 500kS/s, Low-power 10-bit SAR ADC with Digital Averager providing 12-bit Resolution at 30 kS/s
- Software-controlled on-chip reference ranging from 6V to 3.4V
- Temperature sensor and backup battery voltage measurement channel
Debug
- Star Topology AHB-AP Debug Access Port Implementation with Common SW-DP / SWJ-DP Providing Higher Performance than Daisy-chain Topology
- Debug synchronization between both cores (cross triggering to/from each core for Halt and Run Mode)
I/O
- Up to 106 I/O lines with External Interrupt Capability (edge or level sensitivity), Schmitt Trigger, Internal Pull-up/pull-down, Debouncing, Glitch Filtering, and On-die Series Resistor Termination
Package
- 14mm x 14mm LQFP-100; 0.5mm pitch
- 14mm x 14mm TQFP-100; 0.5mm pitch
- 20mm x 20mm TQFP-144; 0.5mm pitch